A comprehensive overview of traditional methods of time interval measurement is given, for instance, in the paper: D.I. Porat, “Review of sub-nanosecond time-interval measurements,” IEEE Transactions on Nuclear Science, vol. 20, no. 5, pp. 36–51.
The most widespread method of time interval measurement is based on a counter that counts reference clock pulses. The dynamic range of the measured interval increases almost exponentially with counter length and is practically unlimited. Resolution of this method is given by the reference clock frequency, which is mainly limited by the speed of the digital circuitry in the counter. This is why the resolution of the counter is not usually better than 1 ns. The measurement accuracy is determined by the accuracy of the reference clock frequency. Thanks to their wide dynamic range and good integral linearity, digital counters are the basis of all methods of time interval measurement with the exception of the measurement of very short time intervals. However, appropriate techniques need to be used to improve their resolution.
A simple method of improving the resolution is the use of several synchronous, phase-shifted clock signals connected to several counters. The accuracy of this method is limited by the accuracy and stability of the phase shift between the individual clock signals.
Substantial improvement of the counter resolution may be achieved by using an analog interpolator, which works on the principle of measurement of the voltage increase on an integrator charged during the measured interval. The interpolator ensures measurement of short intervals from the beginning and the end of the measured interval until the next clock pulse. A simple integrating interpolator, which converts the voltage increase to the time necessary for integrator discharge and thus requires no separate analog-to-digital converter, is often used. Due to the temperature instability of the integration time constant, the integrating interpolator has to be calibrated continuously. Its accuracy is limited by the noise and disturbances in the integrator circuitry, and by the non-linearity of the integrator.
Further interpolation methods are based on the Vernier principle. These methods usually use oscillators started at the beginning and at the end of the measured interval. The oscillator frequency is slightly deviated from the reference clock frequency. The interpolation is based on the measurement of the time elapsed from starting the oscillator until reaching a phase coincidence with the reference clock signal. The resolution is inversely proportional to the frequency deviation of the oscillators. The accuracy is mainly limited by the frequency instability and by the phase fluctuations of the started oscillators.
Recently, interpolation methods based on the propagation of a pulse through a delay line have been developed. The fundamentals of these methods and some of their applications are described, for instance, in the paper: T. E. Rahkonen et al., “The Use of Stabilized CMOS Delay Lines for the Digitization of Short Time Intervals,” IEEE Journal of Solid-State Circuits, vol. 28, no. 8, pp. 887–894 and in the paper: M. Mota et al.: “A High-Resolution Time Interpolator based on a Delay Locked Loop and an RC Delay Line,” IEEE Journal of Solid-State Circuits, vol. 34, no. 10, pp. 1360–1366.
The principle of the use of the delay line is as follows: pulses are supplied to the delay line that consists of numerous identical elements. The logical levels at the outputs of the individual elements are read at the beginning and at the end of the measured interval. The interval length is determined from the number of the elements through which the pulse has passed during the measured time. Due to the temperature dependence of the delay, continuous calibration of the delay line against the reference clock signal is required. The delay in the individual elements can also be maintained at the nominal value by means of PLL or DLL. When PLL is used, the delay line is connected into a ring oscillator. The line delay is controlled so that the ring oscillator remains synchronized with the reference clock signal. In the case of DLL, the delay line is fed by the reference clock signal. The line delay is controlled so as to maintain the input and output signals in phase. The resolution of these methods is given by the delay of the individual elements. If the delay line is based on modern CMOS technology, the resolution is usually in the order of 100 ps.
There are several ways to improve the resolution beyond this limit. One of the possibilities is, once again, the use of the Vernier principle. In this case, two delay lines with a slightly different delay in the individual elements are used, and it is noted on which pair of elements of both delay lines a coincidence of the propagated signals occurs. Another possibility is the use of an array of delay lines that are fed by signals with different delays. This may be achieved, for instance, by feeding the delay line from another delay line tapped at different points and stabilized by DLL or by connecting the array into a multiphase ring oscillator stabilized by PLL. The accuracy of the interpolation by means of the delay line is primarily limited by the differences in the delays of the individual elements. Good linearity may be achieved only if all the line elements have the same delay, which leads to the requirement that the topology of the elements is identical. However, the above condition is difficult to meet in designing the delay line. In the design of the ring delay line it is practically impossible. The accuracy is further limited by the fast components of the noise in the delay line, which cannot be reduced by DLL or PLL stabilization.